1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to crack-arresting structures for through-silicon vias (TSV's) and methods for forming the same.
2. Description of the Related Art
In recent years, the device features of modern, ultra-high density integrated circuits have been steadily decreasing in size in an effort to enhance the overall speed, performance, and functionality of the circuit. As a result, the semiconductor industry has experience tremendous growth due to the significant and ongoing improvements in integration density of a variety of electronic components, such as transistors, capacitors, diodes, and the like. These improvements have primarily come about due to a persistent and successful effort to reduce the critical dimension—i.e., minimum feature size—of components, directly resulting in the ability of process designers to integrate more and more components into a given area of a semiconductor chip.
Improvements in integrated circuit design have been essentially two-dimensional (2D)—that is, the improvements have been related primarily to the layout of the circuit on the surface of a semiconductor chip. However, as device features are being aggressively scaled, and more semiconductor components are being fit onto the surface of a single chip, the required number of electrical interconnects necessary for circuit functionality dramatically increases, resulting in an overall circuit layout that is increasingly becoming more complex and more densely packed. Furthermore, even though improvements in photolithography processes have yielded significant increases in the integration densities of 2D circuit designs, simple reduction in feature size is rapidly approaching the limit of what can presently be achieved in only two dimensions.
As the number of electronic devices on single chip rapidly increases, three-dimensional (3D) integrated circuit layouts, or stacked chip design, have been utilized for some semiconductor devices in an effort to overcome some of the feature size and density limitations associated with 2D layouts. Typically, in a 3D integrated circuit design, two or more semiconductor chips are bonded together, such as through a so-called controlled collapse chip connection (C4) process and the like, so as to form electrical connections between each chip. One method of facilitating the chip-to-chip electrical connections is by use of so-called through-silicon vias, or TSV's. A TSV is a vertical electrical connection element that passes completely through a wafer or semiconductor chip, allowing for more simplified interconnection of vertically aligned electronic devices, and thereby significantly reducing integrated circuit layout complexity, as well as the overall dimensions of a multi-chip circuit. Some of the benefits associated with the interconnect technology enabled by 3D integrated circuit designs include accelerated data exchange, reduced power consumption, and much higher input/output voltage densities.
One illustrative prior art configuration of a semiconductor chip 100 that includes a through-silicon via is schematically illustrated in FIG. 1. As shown in FIG. 1, the semiconductor chip 100 may comprise a substrate 101, which may represent any appropriate carrier material, such as silicon or silicon-based materials, and the like. Additionally, the semiconductor chip 100 may include a semiconductor layer 102 that may be made up of active areas (not shown) in which a plurality of schematically depicted active and/or passive circuit elements 103, such as transistors, capacitors, resistors and the like may be formed, in which case the semiconductor layer 102 may also be referred to as a device layer 102. Depending on the overall design strategy employed for the semiconductor chip 100, the substrate 101 may in some cases be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other instances the 10substrate 101 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided between the device layer 102 and the substrate 101. It should be appreciated that the semiconductor/device layer 102, even if comprising a substantially silicon-based material layer, may include other semiconducting materials, such as germanium, carbon and the like, in addition to appropriate dopant species for establishing the requisite active area conductivity type for the circuit elements 103.
The semiconductor chip 100 shown in FIG. 1 also illustrates a contact layer 104, which may be formed above the device layer 102. The contact layer 104 may be made up of a suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like, and may include a plurality of contact vias 104v. Typically, the contact vias 104v provide conductive electrical connections between one or more of the various circuit elements 103 and a metallization system 105 formed above the contact layer 104. The metallization system 105 may be made up of several metallization layers, such as the metallization layers 105a-h, although it should be appreciated that either more or fewer metallization layers may also be used, depending on the overall device requirements.
Generally, each of the metallization layers 105a-h will be made up of a suitable dielectric insulating material and may have formed therein a plurality of conductive vias 105v and/or a plurality of conductive lines 105L, such as are schematically depicted in FIG. 1, and which, when electrically connected to the circuit elements 103 by way of the contact vias 104v, may thereby form the overall circuit layout (not shown) of the semiconductor chip 100. It should be appreciated, however, that, depending on various device parameters—such as the circuit design, materials of construction, overall processing strategy, and the like—some of the various metallization layers making up a given metallization system may include any one of several combinations of conductive lines 105L and conductive vias 105v. For example, a give metallization layer may include: a level of conductive vias 105v only; a level of conductive lines 105L only (see, e.g., metallization layer 105a in FIG. 1); a level of conductive lines 105L and a level of conductive vias 105v (see, e.g., metallization layers 105b-105h in FIG. 1); or multiple levels of conductive lines 105L and conductive vias 105v. 
The size and spacing of the conductive lines 105L and/or conductive vias 105v used in a given metallization layer may depend on several factors, including, for example, device design process node size (e.g., 45 nm, 32 nm, 22 nm, etc.), as well as the type of dielectric material used for the metallization layer. For example, low-k dielectric materials—such as dielectric materials having a dielectric constant, or k-value, that is approximately 3.0 or lower—may be used when smaller critical dimensions (i.e., thinner or narrower) and a closer spacing (i.e., finer pitch) of the various conductive elements may be desired. On the other hand, more “traditional” silicon-based dielectric materials, such as silicon dioxide, silicon oxynitride, silicon nitride, silicon-carbon-nitride, and the like, which generally have dielectric constants in excess of approximately 3.5, may be used when size and spacing of the conductive lines 105L and/or conductive vias 105v may not be so critical. FIG. 1 schematically depicts an illustrative prior art configuration that includes both respective metallization layers 105a-f that are made up of low-k dielectrics and relatively smaller sized/finer pitched conductive elements 105L, 105v, as well as respective metallization layers 105g-h that are made up of, for example, a silicon dioxide based on TEOS (tetraethyl-orthosilicate) and relatively larger sized/coarser pitched conductive elements 105L, 105v. 
The typical processing steps and materials used to form the circuit elements 103 in the device layer 102, the contact layer 104, and the metallization system 105 are well known in the art, and will not be further herein in detail.
As shown in FIG. 1 the illustrative semiconductor chip 100 may also include one or more through-silicon vias (TSV's) 106 for facilitating electrical connections between two or more stacked chips, as previously described. Typically, after chip processing has been completed, the TSV 106 is a continuous one-piece conductive plug that extends at least from the front side 100f of the substrate 101 to the back side 100b of the substrate 101. In some cases, the TSV 106 may also extend through the contact layer 104 so as to interface with the first metallization layer of the metallization system 105, such as the metallization layer 105a, as shown in FIG. 1. Depending on the various processing parameters associated with forming the TSV 106, such as the depth and width of the via opening (not shown), the material of the substrate 101, and the like, the sidewalls of the TSV 106 may be slightly tapered, as shown in FIG. 1, or they may be substantially vertical with respect to the front and back sides 100f, 100b. The TSV 106 may typically be made up of a suitable conductive material, such as copper or copper-based alloys, and may have an average width 106w ranging between approximately 1 μm and 10 μm. The TSV 106 may also have a through-substrate length 106L of approximately 40-60 μm, although in certain devices the length 106L may be less than 40 μm or greater than 60 μm, depending on the overall device design requirements.
A liner 107 may typically be positioned between the TSV 106 and the substrate 101 so as to electrically isolate the TSV 106, and in some cases, to substantially prevent the material of the TSV 106 from diffusing into the substrate 101, a situation which could create undesirable conducting paths in the semiconductor chip 100, and potentially lead to a commensurate degradation in overall device performance. The material of the liner 107 may have a sidewall thickness in the range of 200-400 nm, and may be made up any suitable insulating dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. Additionally, in some cases a diffusion barrier layer (not shown) having a thickness in the range of 100-200 nm may be formed between the liner 107 and the TSV's 106 so as to prevent the material of the TSV's 106 from diffusing into and/or through the liner 107 and into the substrate 101, the device layer 102, and/or the contact layer 104.
As shown in FIG. 1, a conductive structure 108 may also be formed in the metallization system 105 above the TSV 106. Depending on the overall device requirements, a lower end 108e of the conductive structure 108 may be electrically connected to the upper end 106u of the TSV 106 at the front side 100f of the substrate 101, and may extend from the upper end 106u to the last metallization layer of the metallization system 105, such as the metallization layer 105h. Furthermore, the upper end 108u of the conductive structure 108 may also be electrically connected to a bump structure 112 through a contact pad 110, both of which may be electrically isolated by a passivation layer 111 formed above the last metallization layer 105h of the metallization system 105.
In some cases, the bump structures 112 may be designed to facilitate a bonded electrical connection to another chip or substrate during a chip packaging process, as previously discussed. However, it should also be appreciated that, in at least some devices, bump structures 112 and contact pads 110 may also be provided above the last metallization layer 105h that are electrically connected to one or more of the circuit elements 103 of the semiconductor chip 100, as shown in FIG. 1. In some cases, the bump structures 112 may be made up of an underbump metallization layer 112u and a solder ball 112b, however, it should be noted that other bump structure configurations may also be used, such as pillar bumps and the like. Furthermore, and depending on the overall layout considerations for the semiconductor chip 100, the bump structures 112 may be in direct contact with the contact pads 110, as shown in FIG. 1, whereas in some cases one or more of the bump structures 112 may be positioned a distance away from a respective contact pad 110 and conductively coupled to the pad 110 by a redistribution layer (not shown).
Typically, the conductive structure 108 is made up of a plurality of conductive lines 108L and/or a plurality of conductive vias 108v formed in each of the metallization layers 105a-f. The size, spacing, and design of each of the pluralities of conductive lines 108L and conductive vias 108v may be established in similar fashion as previously described with respect to the conductive lines 105L and conductive vias 105v, giving due consideration to the power transmission requirements between chips for the TSV 106 and conductive structure 108. Additionally, in certain cases, additional conductive elements (not shown) may be provided within one or more of the metallization layers 105a-h that conductively couple the conductive structure 108 to one or more of the conductive lines 105L and/or conductive vias 105v, thereby providing power to at least some of the circuit elements 103.
During normal operation, the temperature of the semiconductor chip 100 will generally increase, due to, for example, the relatively large power consumption by the chip 100. This increased temperature can potentially have an adverse impact on the performance of the circuit elements 103 making up the semiconductor chip 100, due at least in part to the relatively high magnitude of thermal stresses that may be induced in the device layer 102 and the contact layer 104—and consequently on the circuit elements 103—by the TSV 106. These high thermal stresses are generally due to the significant difference in the coefficient of thermal expansion (CTE) between copper—which may be a major material constituent in many TSV's—and that of several of the materials that are commonly used in semiconductor device processing, such as silicon, germanium, silicon dioxide, silicon nitride and the like. For example, Table 1 below lists some approximate representative values of the bulk linear coefficient of thermal expansion (CTE) of several materials that may commonly be used in the manufacture of semiconductor devices, graphically illustrating the difference between the CTE of conductive materials that might commonly be used for forming TSV's, and that of the semiconductor-based materials which might comprise the majority of many device layers and circuit elements making up a typical semiconductor chip, such as the semiconductor chip 100.
TABLE 1Approximate Bulk Linear Coefficients ofThermal Expansion for Selected MaterialsCTESemiconductor-BasedCTEConductive Material(μm/m/° C.)Material(μm/m/° C.)Tungsten4.3Silicon2.6Tantalum6.5Germanium5.8Titanium8.6Silicon-Germanium3.4-5.0Nickel13.0Silicon Dioxide0.5Copper16.6Silicon Nitride3.3Aluminum22.2Silicon Carbide4.0
As can be seen from the approximate CTE data presented in Table 1 above, the coefficient of expansion of a typical conductive material such as copper ranges anywhere from approximately 3 to 30 times greater than the CTE of typical semiconductor-based materials, and in particular is approximately 6 time greater than the CTE of silicon, which may make up the bulk of the substrate 101 of the semiconductor chip 100. Moreover, due to the large amounts of power that are typically transmitted through TSV's—and the correspondingly higher temperatures that may generated as a result—these differences in thermal expansion coefficients may be even further magnified.
During normal device operation, the TSV 106 will typically undergo thermal expansion that is generally oriented in two different directions: a radial expansion 106r across the width 106w of the TSV 106, and an axial expansion 106a over the length 106L. The effects of both the radial expansion 106r and the axial expansion 106a are further discussed below.
In general, the radial expansion 106r will be resisted by the materials of the surrounding substrate 101, device layer 102, and contact layer 104, which, due to the drastic difference in thermal expansion coefficients noted in Table 1 above, will not expand as much as the TSV 106. This radial expansion 106r, resisted by the surrounding materials, often results in correspondingly high thermal stresses 120 in the areas surrounding the TSV 106. As those familiar with the design of sophisticated integrated circuit devices well understand, changes in the stress field surrounding some semiconductor devices, such as field effect transistors and the like, can at least incrementally affect the mobility of holes and/or electrons in the channel region of a device, thus impacting overall performance. Additionally, due to the tremendous size disparity between that of a typical TSV (e.g., sizes on the order of μm's) vs. that of a typical modern integrated circuit element (e.g., sizes on the order of nm's)—a disparity that may approach three orders of magnitude—the thermal stresses 120 induced in any circuit elements 103 that are positioned proximate the TSV's may be even further magnified.
One prior art approach of addressing the local stress effects that may result from the radial expansion 106r of the TSV 106 is to place a “cushion” or “buffer” layer between the TSV 106 and the materials of the surrounding substrate 101, device layer 102, and/or contact layer 104. In some cases, the material of the “buffer” layer may selected so as to have a certain degree of elasticity that may be sufficient to absorb at least some of the differential thermal expansion between the TSV 106 and the surround materials. In some cases, the “buffer” layer may also serve a dual purpose of an insulating layer, and therefore may be used in lieu of the liner 107, provided the material of the “buffer” layer, such as an organic polymer material and the like, provides the requisite electrical isolation function.
For the most part, the prior art “buffer” layer approach is primarily directed to relieving the thermal stress effects that the radial expansion 106r may have on surrounding materials. It does little, however, to address the effects that the axial expansion 106a of the TSV 106 may have on the metallization layers 105a-h of the metallization system 105 formed above the substrate 101. Under the axial expansion 106a, the TSV 106 may induce an uplift load 121 on the first metallization layer 105a, and that uplift load 121 may be transmitted through at least some of the succeeding metallization layers formed thereabove. In some cases, the uplift load 121 caused by the axial expansion 106a may be sufficiently high enough to cause mechanical damage in one or more the metallization layers 105a-h, which may manifest as a crack 130, or a crack-like defect, such as a material layer delamination, and the like. Moreover, the possible creation of these thermally-induced cracks 130 or delamination defects may be compounded in those metallization layers of the metallization system 105 that are made up of low-k dielectric materials (which typically have a lower mechanical strength, and therefore a commensurately lower overall resistance to loads and stresses), thereby possibly resulting in further reduced product performance and/or product life. Not only might these cracks 130 and/or delamination defects generally weaken the areas surround the TSV 106 and the conductive structure 108, they may also tend to propagate and extend throughout the various metallization layers 105a-h of the metallization system 105. Furthermore, such propagating cracks 130 and/or delaminations may affect, and possibly damage, at least some of the conductive lines 105L and/or conductive vias 105v formed in the various metallizations layers 105a-h that define the overall circuit (not shown) of the semiconductor chip 100, thus potentially decreasing the overall chip reliability and/or performance.
Accordingly, there is a need to implement new design strategies to address at least some of the operation and performance issues associated with devices that utilize through-silicon vias for transmitting power between chips. The present disclosure relates to methods and structures for avoiding, or at least reducing, the effects of one or more of the problems identified above.